1. Field of the Invention
The present invention relates to a wide bandgap insulated gate semiconductor device for use with inverters, switching power sources, and the like.
2. Description of Related Art
Due to excellent characteristics such as a high electric breakdown field and high heat transmittance, there is an expectation that wide bandgap semiconductors such as silicon carbide (hereinafter, SiC), gallium nitride (GaN), and diamond will be used for power devices that require a particularly high breakdown voltage and that need to be low loss.
FIG. 8 is a cross-sectional view of a single cell of a conventional planar gate SiC vertical power MOSFET. In FIG. 8, a low impurity concentration n-type drift layer is deposited by SiC epitaxial growth on an n-type SiC semiconductor substrate (n+ substrate 1) with a high impurity concentration. A plurality of p-channel regions 3 are formed on portions of the surface of this low impurity concentration n-type drift layer (n− drift layer 2). A high impurity concentration p-base region (p+ base region 4) for suppressing the spread of the depletion layer is positioned below the p-channel regions 3 in order for the p-channel regions 3 to prevent punch-through during reverse-bias. An n-type region (JFET region 2a) interposed between the respective plurality of p-channel regions 3 and the p+ base region 4 thereunder is connected to the n− drift layer 2.
The n+ source regions 5 and p+ contact regions 6 for low-resistance connection of the respective p-channel regions 3 (p+ base region 4) to a source electrode 9 are formed on respective portions of surface layers of the respective p-channel regions 3. Through an oxidized film 7, a poly-Si gate electrode 8 covers the n+ source region 5 from the end surface thereof along the top of the respective p-channel regions 3 and the JFET region 2a. It is common to make the impurity concentration of the poly-Si gate electrode 8 greater than that of the n− drift layer 2 in order to reduce JFET resistance that occurs in the JFET region 2a interposed between the respective p-channel regions 3 and the p+ base region 4. This JFET resistance occurs due to the depletion layer that spreads during on-bias, which makes the pathway narrower. The source electrode 9 is in low-resistance contact with the surface of the n+ source region 5 and the p+ contact region 6, and a drain electrode 10 is in low-resistance contact with the rear surface on the opposite side of the n+ substrate 1.
The basic operation of the SiC-MOSFET will be described below. If a gate voltage of at least a certain threshold is applied to the poly-Si gate electrode 8, then an inversion layer is formed on the respective p-channel region 3 surface layers directly below the poly-Si gate electrode 8. In this state, if a positive voltage is applied to the drain electrode 10, then an electron path will be formed through the source electrode 9, the n+ source region 5, the surface inversion layer of p-channel regions 3, the JFET region 2a, the n− drift layer 2, the n+ substrate 1, and the drain electrode 10, in this order. In other words, current will flow from the drain electrode 10 towards the source electrode 9.
Meanwhile, if a voltage of less than or equal to a certain threshold is applied to the poly-Si gate electrode 8, then the inversion layer on the surface of the respective p-channel regions 3 will disappear and current will not flow. This basic operation is the same as that of an ordinary MOSFET using a silicon (Si) semiconductor. Due to wide bandgap semiconductors generally having a higher electric breakdown field than a Si semiconductor (approximately 10× higher than 4H—SiC, 11× higher than GaN, and 19× higher than diamond), the impurity concentration in the n− drift layer 2 can be increased and made thin; this makes it possible to realize a device with a higher breakdown voltage and a lower on-resistance than a Si-MOSFET.
Patent Document 1 discloses a MOSFET structure similar to that shown in FIG. 9, which is the cross-sectional view of a single cell of a SiC-MOSFET. Respective trenches have a sufficient depth to reach an n− drift layer 2 from a substrate surface, and both sides of a first trench 20 of a trench gate structure are sandwiched by a source electrode structure constituted of a source electrode 9 that is embedded in a second trench 21. In this trench source electrode structure, the depletion layer spreading from a p+ base region 4 on the bottom of the second trench 21 in the ON state can pinch off charging current flowing to a parasitic transistor (n− drift layer 2 to p-channel region 3 to n+ source region 5). As a result, it is possible to have a device that can withstand an abrupt rise in applied voltage. The reference character 1 represents an n+ substrate, 7 represents a gate insulating film, 8 represents a gate electrode, 10 represents a drain electrode, and 13 represents an interlayer insulating film.
Furthermore, an electrostatic induction-type transistor with a high breakdown voltage (power SIT) and a junction-type field effect transistor with a high breakdown voltage (power JFET) in which the current flowing between the two primary terminals (source and drain) is controlled by the depletion layer that is formed by voltage applied to the gate electrode have been known. These power transistors maintain breakdown voltages by the semiconductor layer located between the gate region formed in the semiconductor layer and the drain region formed on one surface of the semiconductor layer being depleted. (See Patent Document 2.)
Patent Document 3 describes that a region that has a different conductivity from the n− drift layer is formed on the bottom of a trench gate that reaches the n− drift layer, and as a result, the electric field applied to the gate insulating film can be reduced to improve blocking voltage.
Patent Document 4 describes that a floating p− region is provided on a surface layer of an n− drift layer (JFET region) interposed in the n− drift layer along the main surface of a p-base region in a substrate surface facing a MOS gate structure of a planar gate SiC-MOSFET, and as a result, the electric field applied to the gate insulating film in contact with the surface of the JFET region can be suppressed even if the gap with the JFET region is widened.